User Manual
Product Presentation
Technical Note
- TN1404 SR5E1E3, SR5E1E5, SR5E1E7 IO definition (signal description and input multiplexing tables) and device identification registers
- TN1439 SR5 E1 line: getting started with the HRTIM
- TN1464 SR5 E1 Line - Offline self-test
- TN1479 SR5 E1 line – Register protection overview
- TN1483 SR5E1Ex line - ADC accuracy improvement
Data Brief
- DB4256 Stellar SR6 P6 line — 32-bit Arm® Cortex®‑R52+ automotive integration MCU 6x Cortex®‑R52+ cores, 16 MB NVM (2x 15.5 MB “OTA X2”) 2.3 MB RAM, with embedded virtualization, safety and security
- DB4504 Stellar SR6 P7 line — 32-bit Arm® Cortex®‑R52+ automotive integration MCU 6x Cortex®‑R52+ cores, 20 MB NVM (2x 19.5 MB “OTA X2”) 8.2 MB RAM, with embedded virtualization, safety and security
- DB4507 Stellar SR6 G7 line — 32-bit Arm® Cortex®‑R52+ automotive integration MCU 6x Cortex®‑R52+ cores, 20.5 MB NVM (2x 19.5 MB “OTA X2”) 9.1 MB RAM, with embedded virtualization, safety and security
- DB5381 Stellar SR6 G6 line—32-bit Arm® Cortex®‑R52+ automotive integration MCU 4× Cortex®‑R52+ cores, 31 MB xMemory, 3.8 MB RAM, with embedded virtualization, safety, and security
- DB5383 Stellar SR6 P3 line—32-bit Arm® Cortex®‑R52+ automotive integration MCU 3× Cortex®‑R52+ cores, 8 MB NVM (2× 7.5 MB “OTA X2”) 1.3 MB RAM, with embedded virtualization, safety, and security
Application Note
- AN5888 Getting started with the CORDIC accelerator using Stellar E
- AN5941 SR5 E1 Line - Getting started with analog comparators
- AN5949 SR5E1 line - 7 KW EV/HEV on-board-charger reference design
- AN5972 SR5 E1 line - DMA controller and DMA request multiplexer
- AN5990 SR5 E1 line – cross series timer overview